In the more recent systems of this description, a data processor may receive inputs simultaneously from a large number of sources but may require data from only a limited number of these sources in any particular operating phase. Such a situation exists, for example, in the arithmetical units of digital computers performing sequential mathematical operations.
If only one data input per phase is to be utilized, a multiplexer inserted between these sources and a utilization circuit will suffice. If the number of active data inputs per phase is greater but their selection is dictated by a relatively simple program, a conventional priority encoder may be employed for this purpose. In more sophisticated systems, however, no satisfactory solution has been found up to now as far as we are aware. Thus, if an associated control circuit is pre-programmed for each individual phase, the system is not readily adaptable to changes in the program. If, on the other hand, the controller is adjustable to all possible input combinations on instructions from the programmer, its circuitry will have to be highly complex in accordance with prior-art techniques.